High-level synthesis is an automated design process that creates a circuit design from a high level programming language description of an electronic system. The high level programming language description of the electronic system is an algorithmic description. Examples of high level programming languages include, but are not limited to, C, C++, SystemC, and the like. An electronic design automation (EDA) tool operates on the high level programming language description and generates the circuit design. The circuit design may be a register-transfer level hardware description of the electronic system specified using a hardware description language (HDL).
During high level synthesis, one objective is to identify sequential portions of the high level programming language description where parallelism may be introduced. When incorporated into the circuit design, parallelism provides improved resource usage and improved system performance in the resulting circuitry. Many high level programming language descriptions are iterative in nature and utilize complex, programming language constructs such as loops, arrays, and the like. Extracting a dataflow architecture from a high level programming language description having such complex constructs is difficult and not ordinarily performed.